{"slug":"semiconductor-frontiers","topic":"semiconductor-frontiers","title":"Semiconductor Device Frontiers: State of the Field (October 2026)","summary":"Covers gate-all-around and two-dimensional channel transistors, ferroelectric and oxide gate stacks, backside power delivery, and memristive and neuromorphic hardware, as of October 2026. The key takeaway is that device progress is now limited less by single-device switching than by contacts, band-edge disorder, variability and thermal design, so claims that ignore these constraints should be read with care.","version":1,"published_at":"2026-10-30","updated_at":"2026-10-30","stats":{"words":3506,"citations":62,"claims":29,"timeline":18,"benchmarks":9,"open_problems":10,"key_papers":14,"glossary":16},"verification":{"status":"verified","method":"automated figure and citation-relevance triage against cited abstracts, plus targeted AI review with web checks of flagged statements; automated citation resolution","claims_checked":11,"issues_fixed":2,"verified_at":"2026-10-30"},"ai_assisted":true,"price":{"usd":"0.20","protocol":"x402","network":"eip155:84532","asset":"USDC"},"url":"https://space-kitty.com/dossiers/semiconductor-frontiers","preview_url":"https://space-kitty.com/api/v1/dossiers/semiconductor-frontiers/preview","purchase_url":"https://space-kitty.com/api/v1/dossiers/semiconductor-frontiers","toc":[{"level":2,"text":"Executive summary","anchor":"executive-summary"},{"level":2,"text":"Background and core concepts","anchor":"background-and-core-concepts"},{"level":2,"text":"Timeline of key milestones","anchor":"timeline-of-key-milestones"},{"level":2,"text":"State of the art","anchor":"state-of-the-art"},{"level":3,"text":"Gate-all-around and three-dimensional channel control","anchor":"gate-all-around-and-three-dimensional-channel-control"},{"level":3,"text":"Two-dimensional channels, contacts and growth","anchor":"two-dimensional-channels-contacts-and-growth"},{"level":3,"text":"Oxide channels and gate stacks","anchor":"oxide-channels-and-gate-stacks"},{"level":3,"text":"Memristors and in-memory computing","anchor":"memristors-and-in-memory-computing"},{"level":3,"text":"Neuromorphic systems","anchor":"neuromorphic-systems"},{"level":3,"text":"Backside power delivery and packaging","anchor":"backside-power-delivery-and-packaging"},{"level":3,"text":"Quantitative benchmarks","anchor":"quantitative-benchmarks"},{"level":2,"text":"Open problems and active debates","anchor":"open-problems-and-active-debates"},{"level":2,"text":"Major programs and players","anchor":"major-programs-and-players"},{"level":2,"text":"Outlook: what to watch (next 12-18 months)","anchor":"outlook-what-to-watch-next-12-18-months"},{"level":2,"text":"Key papers","anchor":"key-papers"},{"level":2,"text":"Glossary","anchor":"glossary"}],"sample_claims":["Gate-all-around devices surround the channel with the gate on all sides; nanowire and nanosheet variants stack channels vertically.","Conventional thermionic transport limits subthreshold swing to about 60 mV/dec at 300 K."],"includes":["markdown","claims","timeline","benchmarks","open_problems","key_papers","glossary","bibliography"],"citation_count":62,"how_to_buy":"GET https://space-kitty.com/api/v1/dossiers/semiconductor-frontiers with an x402 client ($0.20, USDC on Base Sepolia (testnet))."}